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WEDPZ512K72V-XBX
512K x 72 Synchronous Pipeline Burst ZBL SRAM
FEATURES
Fast clock speed: 150, 133, and 100MHz Fast access times: 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.8ns, 4.2ns, and 5.0ns High performance 3-1-1-1 access rate 3.3V 5% power supply I/O supply voltage 3.3V or 2.5V Common data inputs and data outputs Byte write enable and global write control Six chip enables for depth expansion and address pipeline Internally self-timed write cycle Burst control pin (interleaved or linear burst sequence) Automatic power-down for portable applications Commercial, industrial and military temperature ranges Packaging: * 152 PBGA package 17 x 23mm
DESCRIPTION
The WEDC SyncBurst - SRAM employs high-speed, low-power CMOS design that is fabricated using an advanced CMOS process. WEDC's 32Mb SyncBurst SRAMs integrate two 512K x 36 SSRAMs into a single BGA package to provide 512K x 72 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The ZBL or Zero Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low." Asynchronous inputs include the sleep mode enable (ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals.
* Product is subject to change without notice.
FUNCTIONAL BLOCK DIAGRAM
512K x 36 SSRAM
A0-18 BWa# SA BWa# BWb# BWc# BWd# WE0# OE0# CLK CKE# CS1# CS2# CS2 ADV LBO# ZZ DQPA DQA0-7 DQPB DQB0-7 DQPC DQC0-7 DQPD DQD0-7 DQPA DQA0-7 DQPB DQB0-7 DQPC DQC0-7 DQPD DQD0-7
BENEFITS
30% space savings compared to equivalent TQFP solution Reduced part count 24% I/O reduction Laminate interposer for optimum TCE match Low Profile Reduce layer count for board routing Suitable for hi-reliability applications User configurable as 1M x 36 or 2M x 18 Upgradable to 1M x 72 (contact factory for availability)
BWb# BWc# BWd# WE0# OE0# CLK0 CKE0# CS10# CS20# CS20 ADV0 LBO# ZZ
512K x 36 SSRAM SA BWe# BWf# BWg# BWh# WE1# OE1# CLK1# CKE1# CS11# CS21# CS21 ADV1 BWa# BWb# BWc# BWd# WEO# OEO# CLK CKE CS1# CS2# CS2 ADV LBO# ZZ
DQPA DQA0-7 DQPB DQB0-7 DQPC DQC0-7 DQPH DQD0-7 DQPE DQE0-7 DQPF DQF0-7 DQPG DQG0-7 DQPH DQH0-7
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PIN CONFIGURATION
(TOP VIEW) 1 A B C D E F G H J K L M N P R T U
-
WEDPZ512K72V-XBX
2 ADV0 WE0# CS20# BWb# BWd# CS20 DQC0 DQC1 A6 DQF4 DQF5 OE1# WE1# CS21# BWf# BWh# CS21
3 OE0# DQb7 DQc2 DQC3 DQC4 DQC5 DQC7 DQC6 DQF2 FQF3 DQF6 DQF7 DQPF DQF1 DQF0 DQG0 DQG3
4 DQb2 DQb5 DQpc VSS VCCQ VCCQ VSS VCC VSS VCC VCC VSS VCCQ VSS DQG1 DQG2 DQPG
5 DQb4 DQb3 DQpb VSS VCCQ VCCQ VCC VCC VSS VCC VCC VCCQ VCCQ VSS DQG4 DQG5 DQG6
6 DQb6 DQb0 DQb1 VSS VCCQ VSS VCC VCC VSS VCC VSS VCCQ VCCQ VSS DQH1 DQH0 DQG7
7 dnu DQa7 DQd7 DQD6 DQD5 DQD4 DQD3 DQD2 DQD1 DQD0 DQE6 DQE7 DQE5 DQE4 DQH2 DQH4 DQH3
8 DQa6 DQa3 DQa4 DQA5 DQPD DNU* A1 A2 A4 A14 A12 A10 DQE3 DQE2 DQE1 DQH7 DQH5
9 DQa2 DQa1 DQa0 DQPA ZZ A0 A3 A5 A16 A15 A13 A11 LBO# DQE0 DQPE DQPH DQH6
CKE0# CLK0 BWa# BWc# CS10# A7 A18 A9 A8 A17 ADV1 CKE1# CLK1 BWe# BWg# CS11#
NOTE: DNU means Do Not Use and are reserved for future use. * Pin F8 reserved for A19 upgrade to 1M x 72
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FUNCTION DESCRIPTION
The WEDPZ512K72V-XBX is an ZBL SSRAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE#, LBO# and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable (CKE#) pin allows the operation of the chip to be suspended as long as necessary. When CKE# is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NBL SSRAM latches external address and initiates a cycle when CKE and ADV are driven low at the rising edge of the clock. Output Enable (OE#) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE# is driven low, the write enable input signals WE# are driven high, and ADV driven low. The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. During read operation OE# must be driven low for the device to drive out the requested data.
WEDPZ512K72V-XBX
Write operation occurs when WE# is driven low at the rising edge of the clock. BW#[h:a] can be used for byte write operation. The pipe-lined ZBL SSRAM uses a latelate write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE# and address are registered, and the data associated with that address is required two cycles later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO# pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after two cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates after two cycles of wake up time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO# = High) Case 1 LBO# Pin High A1 0 0 1 Fourth Address 1 A0 0 1 0 1 Case 2 A1 0 0 1 1 A0 1 0 1 0 Case 3 A1 1 1 0 0 A0 0 1 0 1 Case 4 A1 1 1 0 0 A0 1 0 1 0 Fourth Address LBO# Pin High Case 1 A1 0 0 1 1 A0 0 1 0 1 (Linear Burst, LBO# = Low) Case 2 A1 0 1 1 0 A0 1 0 1 0 Case 3 A1 1 1 0 0 A0 0 1 0 1 Case 4 A1 1 0 0 1 A0 1 0 1 0
First Address
First Address
NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.
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TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CEx# H X L X L X L X L X X ADV L H L H L H L H L H X WE# X X H X H X L X L X X BWx# X X X X X X L L H H X OE# X X L L H H X X X X X CKE# L L L L L L L L L L H CLK
- - - - - - - - - - -
WEDPZ512K72V-XBX
Address Accessed N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address
Operation Deselect Continue Deselect Begin Burst Read Cycle Continue Burst Read Cycle NOP/Dummy Read Dummy Read Begin Burst Write Cycle Continue Burst Write Cycle NOP/Write Abort Write Abort Ignore Clock
NOTES: 1. X means "Don't Care." 2. The rising edge of clock is symbolized by (-). 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WRITE# = L means Write operation in WRITE TRUTH TABLE. WRITE# = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins (ZZ and OE). 6. CEx# refers to the combination of CS1#, CS2 and CS2#.
WRITE TRUTH TABLE
WE# H L L L L L L BWa# X L H H H L H BWb# X H L H H L H BWc# X H H L H L H BWd# X H H H L L H Operation Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write Abort/NOP
NOTES: 1. X means "Don't Care." 2. All inputs in this table must meet setup and hold time around the rising edge of CLK (-). 3. Replace BWa# with BWe#, BWb#, with BWf#, BWc# with BWg# and BWd# with BWh# for operation of IC2.
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ABSOLUTE MAXIMUM RATINGS*
VIN Voltage or any other pin relative hovss Voltage on VCC Supply Relative to VSS Storage Temperature (BGA) Maximum Operating Junction Temperature -0.3V to +4.6V -0.3V to +4.6V -55C to +150C 125C
WEDPZ512K72V-XBX
* Stress greater than those listed under "Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Electrical Characteristics
-55C TA + 125C Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage I/O Power Supply (3.3V) I/O Power Supply (2.5V) Symbol VIH VIL IIL IOL VOH VOL VCC VCCQ VCCQ VCC = Max, 0V VIN VCC Output(s) Disabled, VOUT = VSS to VCCQ IOH = -4.0mA IOH = -1mA (2.5v I/O) IOL = 8.0mA (3.3V I/O) IOL = 1.0 mA (2.5v I/O) Conditions 3.3V I/O 2.5V I/O 3.3V I/O 2.5 I/O Min 2.0 1.7 -0.3 -0.3 -4 -2 2.4 2.0 -- -- 3.135 3.135 2.375 Max VCC +0.5 VCC +0.5 0.7 0.7 +4 +2 -- -- 0.4 0.4 3.465 3.465 2.9 Units V V A A V V V V V V V Notes 1 1 2 1 1 1 1 1
NOTES: 1. All voltages referenced to VSS (GND) 2. ZZ pin has an internal pull-up, and input leakage = 20 A.
DC CHARACTERISTICS
-55C TA + 125C Description Power Supply Current: Operating Power Supply Current: Standby Clock Running Standby Current Symbol IDD ISB2 ISB Conditions Device Selected; All Inputs VIL or VIH; Cycle Time TCYC MIN; VCC = MAX; Output Open Device Deselected; VCC = MAX; All Inputs VIL or VIH All Inputs Static; CLK Frequency = MAX Output Open, ZZ VCC - 0.2V Device Deselected; VCC = MAX; All Inputs VSS + 0.2 or VCC - 0.2; f = max ; ZZ VIL 150 MHz (Max) 700 120 200 133 MHz (Max) 650 120 180 100 MHz (Max) 600 120 160 Units mA mA mA Notes 1
NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading.
BGA CAPACITANCE
TA = + 25C, f = 1MHz Description Control Input Capacitance (LBO#, zz) Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance Symbol CIC CI CO CA CCK Max 16 8 10 16 6 Units pF pF pF pF pF Notes 1 1 1 1 1
THERMAL RESISTANCE
Parameter Thermal Resistance: Die Junction to Ambient Thermal Resistance: Die Junction to Ball Thermal Resistance: Die Junction to Case Symbol JA JB JC Max 28.1 16.0 7.1 Unit C/W C/W C/W
Note: Refer to Application Note "PBGA Thermal Resistance Corrleation" for further information regarding WEDC's thermal modeling.
NOTES: 1. This parameter is not tested but guaranteed by design.
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AC CHARACTERISTICS
-55C TA + 125C 150MHz Parameter Clock Time Clock Access Time Output enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High CKE Setup to Clock High Data Setup to Clock High Write Setup to Clock High Address Advance to Clock High Chip Select Setup to Clock High Address Hold to Clock high CKE Hold to Clock High Data Hold to Clock High Write Hold to Clock High Address Advance to Clock High Chip Select Hold to Clock High Symbol tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tCES tDS tWS tADVS tCSS tAH tCEH tDH tWH tADVH tCSH Min 6.7 -- -- 1.5 1.5 0.0 -- -- 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 3.8 3.8 -- -- -- 3.0 3.0 -- -- -- -- -- -- Min 7.5 -- -- 1.5 1.5 0.0 -- -- 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5
WEDPZ512K72V-XBX
133MHz Max 4.2 4.2 -- -- -- 3.5 3.5 -- -- -- -- -- --
100MHz Min 10.0 -- -- 1.5 1.5 0.0 -- -- 3.0 3.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max 5.0 5.0 -- -- -- 3.5 3.5 -- -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
NOTES: 1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CSx# is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled. 3. A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low. Both cases must meet setup and hold times.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Value 0 to 3.6V 1.0V/ns 1.5V See Output Load (A & B)
OUTPUT LOAD (A)
Dout Zo=50 RL=50 VL=1.5V 50pF*
Dout
OUTPUT LOAD (B)
FOR tlzc, tlzoe, thzoe, and thzc
+3.3V for 3.3V I/O, +2.5V for 2.5V I/O 319/1667
VL = 1.5V for 3.3V I/O VCCQ/2 for 2.5V I/O
*Including Scope and Jig Capacitance
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353/1538
5pF*
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SNOOZE MODE
SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time Z is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE.
WEDPZ512K72V-XBX
When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed.
Snooze Mode
Description Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current Conditions ZZ VIH Symbol ISB2Z tZZ tRZZ tZZI tRZZI Min Max 20 2 2 0 Units mA cycle cycle cycle ns
2
FIGURE 2 - SNOOZE MODE TIMING DIAGRAM
CLOCK
tZZ
ZZ
tRZZ
tZZI
ISUPPLY
tRZZI
IISB2Z
ALL INPUTS (except ZZ)
Deselect or Read Only
DESELECT or READ Only
Normal Operation Cycle
Output (Q) HIGH-Z
DON'T CARE
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WEDPZ512K72V-XBX
FIGURE 3 - TIMING WAVEFORM OF READ CYCLE
tCH
tCL
CLKX
tCYC tCES tCEH
CKEX#
tAS
tAH A1 A2 A3
Address
tWS
tWH
WRITE#
tCSS
tCSH
CSx#
tADVS tADVH
ADVX
OE#
tOE tLZOE tHZOE Q1-1 tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 tHZC Q3-4
Data Out
NOTES:
WRITE# = L means WEX# = L, and BWX# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#.
Don't Care Undefined
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WEDPZ512K72V-XBX
FIGURE 4 - TIMING WAVEFORM OF WRITE CYCLE
tCH
tCL
CLKX
tCES tCEH tCYC
CKEX#
Address
A1
A2
A3
WRITE#
CSx#
ADVX
OE#
tDS tDH D3-2 D3-3 D3-4
Data In
tHZOE
D1-1
D2-1
D2-2
D2-3
D2-4
D3-1
Data Out
Q0-3
Q0-4
NOTES:
WRITE# = L means WEX# = L, and BWX# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#.
Don't Care
Undefined
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WEDPZ512K72V-XBX
FIGURE 5 - TIMING WAVEFORM OF SINGLE READ/WRITE
tCH
tCL
CLKX
tCES tCEH tCYC
CKEX#
Address
A1
A2
A3
A4
A5
A6
A7
A8
A9
WRITE#
CSx#
ADVX
OE#
tOE tLZOE
Data Out
Q1 tDS tDH D2
Q3
Q4
Q6
Q7
Data In
D5
NOTES:
WRITE# = L means WEX# = L, and BWX# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#.
Don't Care
Undefined
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WEDPZ512K72V-XBX
FIGURE 6 - TIMING WAVEFORM OF CKE OPERATION
tCH
tCL
CLKX
tCES tCEH tCYC
CKEX#
Address
A1
A2
A3
A4
A5
A6
WRITE#
CSx#
ADVX
OE#
tCD tLZC tHZC Q1 tDS tDH D2 Q3 Q4
Data Out
Data In
NOTES:
WRITE# = L means WEX# = L, and BWX# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#.
Don't Care Undefined
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WEDPZ512K72V-XBX
FIGURE 7 - TIMING WAVEFORM OF CE OPERATION
tCH
tCL
CLKX
tCES tCEH tCYC
CKEX#
Address
A1
A2
A3
A4
A5
WRITE#
CSx#
ADVX
OE#
tOE tLZOE tHZC Q1 Q2 tDS tDH tCD tLZC Q4
Data Out
Data In
D3
D5
NOTES:
WRITE# = L means WEX# = L, and BWX# = L CSx# refers to the combination of CS10#, CS20 and CS20#, or CS11#, CS21 and CS21#.
Don't Care Undefined
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WEDPZ512K72V-XBX
PACKAGE DIMENSION: - 152 BUMP PBGA
Bottom View
9 8 7 6 5 4 3 2 1 A B C D E F G
0.762 (0.030) NOM
23.1 (0.909) MAX 20.32 (0.800) NOM 1.27 (0.050) NOM
H J K L M N P R T U
1.27 (0.050) NOM 10.16 (0.400) NOM 17.1 (0.673) MAX
0.61 (0.024) NOM 2.03 (0.080) MAX
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
WED P Z 512K 72 V - XXX B X
DEVICE GRADE: M = Military I = Industrial C = Commercial PACKAGE: B = 152 Plastic Ball Grid Array (PBGA) FREQUENCY (MHz) 100 = 100MHz 133 = 133MHz 150 = 150MHz 3.3 V Voltage CONFIGURATION, 512K x 72 SSRAM ZBL PLASTIC WHITE ELECTRONIC DESIGNS CORP.
February 2006 Rev. 7
-55C to +125C -40C to +85C 0C to +70C
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Document Title
512K x 72 Synchronous Pipeline Burst ZBL SRAM
WEDPZ512K72V-XBX
Revision History Rev #
Rev 0 Rev 1
History
Initial Release Changes (Pg. 1) 1.1 Change status from Advanced to Preliminary Changes (Pg. 1, 2) 1.1 Block Diagram: Address lines should be A0-18 1.2 Pin Configuration: Add Note *Pin F8 reserved for A19 upgrade to 1Mx72. Changes (Pg. 1, 5) 1.1 BGA Capacitance: Remove references to temperature in individual conditions 1.2 Change CI from 10pF to 8pF 1.3 Change CA from 20pF to 16pF 1.4 Change CCK from 7pF to 6pF 1.5 Add Control Input Capacitance (CIC) 16pF Changes (Pg. 5) 1.1 Add Thermal Resistance table 1.2 Update current values 1.3 Update package mechanical drawing Changes (Pg. 1, 5, 14) 1.1 Remove reference to Preliminary status 1.2 Add Maximum Operating Junction Temperature of 125C Changes (Pg. 1, 13, 14) 1.1 Change mechanical drawing to new style Changes (Pg. 1, 5, 14) 1.1 Change VIL 3.3V ti 0.7V maximum 1.2 Change status to Final
Release Date
May 2001 March 2001
Status
Advanced Preliminary
Rev 2
March 2002
Preliminary
Rev 3
November 2002
Preliminary
Rev 4
May 2003
Preliminary
Rev 5
June 2003
Preliminary
Rev 6
November 2003
Preliminary
Rev 7
February 2006
Final
February 2006 Rev. 7
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